the highest of claims that their cpu being faster than 52 H200s, is likely in reference to the inferencing performance of their TPU, which is basically an ASIC designed to do that and only that. ASICs are known to be much faster than general computing because the hardware is optimized for that one specific task.
the highest of claims that their cpu being faster than 52 H200s, is likely in reference to the inferencing performance of their TPU, which is basically an ASIC designed to do that and only that. ASICs are known to be much faster than general computing because the hardware is optimized for that one specific task.
it will be of little use to BOINC projects.
So another question is do they have a general GPU mode? I guess I need to re-read that.
Tom M
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)
If this is true it would be a game changer. And it would put serious price pressure on Nvidia's stock valuation. Much less the price of its AI GPU's and Hopper/GPU combo's. I wonder if it would also do a number on Amd and Intel's AI aspirations.
Tom M
Now if they could actually get anything on the market....
We have been eagerly awaiting a CPU from them for years and they have yet to release one even though they have talked about their amazing product for years. IF they do every release a CPU or GPU it MIGHT be amazing. But, they do not have a proven track record.
I think I saw a claimed timeline of before the end of 2024. So they need to put up or shut up :)
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)
Way back when, say 50 some years ago. Ibm got a major performance boost on their DASD units (really big hard disks) when they went to fixed block lengths for reading/writing. And the DASD were cheaper to manufacturer.
Are there systematic ways you could simplify the x86 architecture and instruction code without making the binaries incompatible? Or alternatively once you had it built recompile from source code?
The goal would be to gain speed and efficiency with out going whole hog RISC.
Tom M
---edit---
Or might a compiler using a subset of the IC produce a more efficient binary?
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)
"Are there systematic ways you could simplify the x86 architecture and instruction code without making the binaries incompatible?" :
Nope. I think there's a contradiction in the question, or it depends upon what you are keeping constant when you 'simplify'. If you simplify the instruction codes then you will get to binary incompatibility. That is, prior binaries will not run for some instructions on the simplified encoding. As for the architecture, that's already been done while keeping binary compatibility on executables. For instance, microcode is an 'inner' layer with respect to the 'outer' layer of instruction encoding. It makes a CISC be implemented by a RISC. RISC and CISC are in truth arbitrary/relative terms for regions on a spectrum of universal machine designs.
"Or alternatively once you had it built recompile from source code?" :
Alan Turing would say yes1, in that any universal machine2 can mimic any other universal machine - in it's sequence of outputs for a given sequence of inputs - with the rider that it may do that mimicry in a different time frame and/or with a different amount of storage. Generically speed and storage are tradeable one for the other.
"Or might a compiler using a subset of the IC produce a more efficient binary?" :
Probably not in general as per the speed/storage trade. It kind of depends on what you mean by more efficient. Faster ie. fewer total cycles? Smaller footprint when stored? What are the constraints?
ASIDE : These concerns will be examined more closely in the near future, as I think we have approached the end of Moore's law : which used to solve any efficiency problem simply by waiting for faster silicon to be manufactured. The masking of silicon features is well into the UV realm and any (much) further reduction in wavelength will begin to impose upon the lattice substrate etc.
To enable SVM (Virtual Machines) when your not using any VM's or not?
I wonder if there might be a slight speedup with SVM disabled?
It is clear there is a task speed up when you disable SMT (Hyperthreading). But depending on the actual work load mix total production may not go up and might go down.
Tom M
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)
the highest of claims that
)
the highest of claims that their cpu being faster than 52 H200s, is likely in reference to the inferencing performance of their TPU, which is basically an ASIC designed to do that and only that. ASICs are known to be much faster than general computing because the hardware is optimized for that one specific task.
it will be of little use to BOINC projects.
_________________________________________________________________________
Ian&Steve C. wrote: the
)
So another question is do they have a general GPU mode? I guess I need to re-read that.
Tom M
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)
Boca Raton Community HS
)
I think I saw a claimed timeline of before the end of 2024. So they need to put up or shut up :)
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)
Way back when, say 50 some
)
Way back when, say 50 some years ago. Ibm got a major performance boost on their DASD units (really big hard disks) when they went to fixed block lengths for reading/writing. And the DASD were cheaper to manufacturer.
Are there systematic ways you could simplify the x86 architecture and instruction code without making the binaries incompatible? Or alternatively once you had it built recompile from source code?
The goal would be to gain speed and efficiency with out going whole hog RISC.
Tom M
---edit---
Or might a compiler using a subset of the IC produce a more efficient binary?
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)
"Are there systematic ways
)
I will give this a go.
"Are there systematic ways you could simplify the x86 architecture and instruction code without making the binaries incompatible?" :
"Or alternatively once you had it built recompile from source code?" :
"Or might a compiler using a subset of the IC produce a more efficient binary?" :
ASIDE : These concerns will be examined more closely in the near future, as I think we have approached the end of Moore's law : which used to solve any efficiency problem simply by waiting for faster silicon to be manufactured. The masking of silicon features is well into the UV realm and any (much) further reduction in wavelength will begin to impose upon the lattice substrate etc.
Cheers, Mike.
1. See ON COMPUTABLE NUMBERS, WITH AN APPLICATION TO THE ENTSCHEIDUNGSPROBLEM which is more than a bit dense in parts. But it is the underlying seminal work for modern computing devices and algorithms. See also the works of John von Neumann.
2. See Part 1 of the above paper, that part which is titled "Computing machines".
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Thank you Mike. I strongly
)
Thank you Mike. I strongly suspected your answer when I posted my question. But it was good of you to expand your answer from "No".
I appreciate it.
Tom M
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)
To enable SVM (Virtual
)
To enable SVM (Virtual Machines) when your not using any VM's or not?
I wonder if there might be a slight speedup with SVM disabled?
It is clear there is a task speed up when you disable SMT (Hyperthreading). But depending on the actual work load mix total production may not go up and might go down.
Tom M
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor)