Thanks for sharing that, that's a very good article. What it demonstrates is that for a given task there is an irreducuble algorithmic complexity, with the choice to put that into the instruction set architecture and/or the implementing hardware (compilation aside). But then if you change the task .....
I never really understood RISC vs CISC when it first came up - yes, I am that old - so now I'm pleased to hear it now doesn't matter. A non-question for a non-problem. But it is right in saying that the CPU will nearly always beat DRAM response, the speed of light being what it is : you can consider circuitry as fancy waveguides if you like and proximal beats distal nearly always. Now if only we had an ASIC for every eventuality. :-)
Cheers, Mike.
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Thanks for sharing that, that's a very good article. What it demonstrates is that for a given task there is an irreducuble algorithmic complexity, with the choice to put that into the instruction set architecture and/or the implementing hardware (compilation aside). But then if you change the task .....
I never really understood RISC vs CISC when it first came up - yes, I am that old - so now I'm pleased to hear it now doesn't matter. A non-question for a non-problem. But it is right in saying that the CPU will nearly always beat DRAM response, the speed of light being what it is : you can consider circuitry as fancy waveguides if you like and proximal beats distal nearly always. Now if only we had an ASIC for every eventuality. :-)
Cheers, Mike.
What would be cool is an on the fly re-programmable ASIC, then each need could be addressed by the programmers and handled by the device. Probably too expensive to make and then repair when it breaks but cool anyway.
Thanks for sharing that, that's a very good article. What it demonstrates is that for a given task there is an irreducuble algorithmic complexity, with the choice to put that into the instruction set architecture and/or the implementing hardware (compilation aside). But then if you change the task .....
I never really understood RISC vs CISC when it first came up - yes, I am that old - so now I'm pleased to hear it now doesn't matter. A non-question for a non-problem. But it is right in saying that the CPU will nearly always beat DRAM response, the speed of light being what it is : you can consider circuitry as fancy waveguides if you like and proximal beats distal nearly always. Now if only we had an ASIC for every eventuality. :-)
Cheers, Mike.
What would be cool is an on the fly re-programmable ASIC, then each need could be addressed by the programmers and handled by the device. Probably too expensive to make and then repair when it breaks but cool anyway.
1. if it was reprogrammable/reconfigurable, it would no longer be an 'ASIC'
2. what you're describing is exactly what a FPGA is.
Thanks for sharing that, that's a very good article. What it demonstrates is that for a given task there is an irreducuble algorithmic complexity, with the choice to put that into the instruction set architecture and/or the implementing hardware (compilation aside). But then if you change the task .....
I never really understood RISC vs CISC when it first came up - yes, I am that old - so now I'm pleased to hear it now doesn't matter. A non-question for a non-problem. But it is right in saying that the CPU will nearly always beat DRAM response, the speed of light being what it is : you can consider circuitry as fancy waveguides if you like and proximal beats distal nearly always. Now if only we had an ASIC for every eventuality. :-)
Cheers, Mike.
What would be cool is an on the fly re-programmable ASIC, then each need could be addressed by the programmers and handled by the device. Probably too expensive to make and then repair when it breaks but cool anyway.
1. if it was reprogrammable/reconfigurable, it would no longer be an 'ASIC'
2. what you're describing is exactly what a FPGA is.
Since I am now officially old, and my processor is slowing down, I go in next week to get a RISC Brain installed.
Mike Hewson promised me it would work fine and reduce overheating.
Yeah, but I should mention the mandatory 25 kg palladium heatsink. With a bit of machining it could replace his hair with radiation fins, like mine. In the shape of an Elvis bouffant perhaps, or a good ole 70's mullet ? Marine induction cut ?? {..... ducks & runs}
Regards, Mike
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Since I am now officially old, and my processor is slowing down, I go in next week to get a RISC Brain installed.
Mike Hewson promised me it would work fine and reduce overheating.
Yeah, but I should mention the mandatory 25 kg palladium heatsink. With a bit of machining it could replace his hair with radiation fins, like mine. In the shape of an Elvis bouffant perhaps, or a good ole 70's mullet ? Marine induction cut ?? {..... ducks & runs}
Regards, Mike
OMG I'm trying to breath from laughing so hard.
Just so you know, the "Marine Induction Cut" is officially called a "High and Tight".
Fair warning, a long time from now, when you are laying in bed waiting to meet your maker, I'm going to show up and say, "You can't go yet, I still don't have my heatsink!"
Happy I'm Hibernating Because It's Black Friday, Phil
Edit: Correction. During induction they take it all off. During boot camp, as your hair grows they let it grow on top a bit but still take all the sides and back off. Hence the high and tight. I still did a high and tight for about two years into my career.
Ooops, on today's spot price for Palladium, 25 kg is worth about $1.25M AUD ....
Would that make his brain "golden"?
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor) I want some more patience. RIGHT NOW!
Thanks for sharing that,
)
Thanks for sharing that, that's a very good article. What it demonstrates is that for a given task there is an irreducuble algorithmic complexity, with the choice to put that into the instruction set architecture and/or the implementing hardware (compilation aside). But then if you change the task .....
I never really understood RISC vs CISC when it first came up - yes, I am that old - so now I'm pleased to hear it now doesn't matter. A non-question for a non-problem. But it is right in saying that the CPU will nearly always beat DRAM response, the speed of light being what it is : you can consider circuitry as fancy waveguides if you like and proximal beats distal nearly always. Now if only we had an ASIC for every eventuality. :-)
Cheers, Mike.
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Mike Hewson wrote: Thanks
)
What would be cool is an on the fly re-programmable ASIC, then each need could be addressed by the programmers and handled by the device. Probably too expensive to make and then repair when it breaks but cool anyway.
mikey wrote: Mike Hewson
)
1. if it was reprogrammable/reconfigurable, it would no longer be an 'ASIC'
2. what you're describing is exactly what a FPGA is.
_________________________________________________________________________
Ian&Steve C. wrote: mikey
)
I did not know that, interesting.
Since I am now officially
)
Since I am now officially old, and my processor is slowing down, I go in next week to get a RISC Brain installed.
Mike Hewson promised me it would work fine and reduce overheating.
I thought I was wrong once, but I was mistaken.
Phil wrote: Since I am now
)
LOL!!!
Phil wrote: Since I am now
)
Yeah, but I should mention the mandatory 25 kg palladium heatsink. With a bit of machining it could replace his hair with radiation fins, like mine. In the shape of an Elvis bouffant perhaps, or a good ole 70's mullet ? Marine induction cut ?? {..... ducks & runs}
Regards, Mike
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Mike Hewson wrote:Phil
)
OMG I'm trying to breath from laughing so hard.
Just so you know, the "Marine Induction Cut" is officially called a "High and Tight".
Fair warning, a long time from now, when you are laying in bed waiting to meet your maker, I'm going to show up and say, "You can't go yet, I still don't have my heatsink!"
Happy I'm Hibernating Because It's Black Friday, Phil
Edit: Correction. During induction they take it all off. During boot camp, as your hair grows they let it grow on top a bit but still take all the sides and back off. Hence the high and tight. I still did a high and tight for about two years into my career.
I thought I was wrong once, but I was mistaken.
Ooops, on today's spot price
)
Ooops, on today's spot price for Palladium, 25 kg is worth about $1.25M AUD ....
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Mike Hewson wrote: Ooops, on
)
Would that make his brain "golden"?
A Proud member of the O.F.A. (Old Farts Association). Be well, do good work, and keep in touch.® (Garrison Keillor) I want some more patience. RIGHT NOW!