AMD reveals plans for "SSE5"

Bikeman (Heinz-Bernd Eggenstein)
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Topic 193090

Hi!

AMD published details about it's plans for "SSE5" instruction set extensions for it's 2nd generation of Barcelona, expected not earlier than in 2009 (so no need to hurry, Akos :-) ):

pdf download

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Akos Fekete
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AMD reveals plans for "SSE5"

Quote:
AMD published details about it's plans for "SSE5" instruction set extensions for it's 2nd generation of Barcelona, expected not earlier than in 2009 (so no need to hurry, Akos :-) ):


Oh, yes...

SSE5 has a really good feature. There are four-operand instructions!
But only with one memory operand, of course...

...and some crazy instructions too.
eg.: PHADDBQ (Packed Horizontal Add Signed Byte to Signed Quadword)
It does exactly 14 additions. Really crazy. :)

Bikeman (Heinz-Bernd Eggenstein)
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RE: RE: AMD published

Message 72740 in response to message 72739

Quote:
Quote:
AMD published details about it's plans for "SSE5" instruction set extensions for it's 2nd generation of Barcelona, expected not earlier than in 2009 (so no need to hurry, Akos :-) ):

Oh, yes...

SSE5 has a really good feature. There are four-operand instructions!
But only with one memory operand, of course...

...and some crazy instructions too.
eg.: PHADDBQ (Packed Horizontal Add Signed Byte to Signed Quadword)
It does exactly 14 additions. Really crazy. :)

It's strange that things like y := a*x +b in a single vector instruction did not appear earlier in Intel FPUs.

CU

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Bikeman (Heinz-Bernd Eggenstein)
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BTW, Akos, you are seriously

BTW, Akos, you are seriously overclocking your equipment, right?

Did you ever experience a fault that looks like the one quoted here by overclocking a bit too much? This is a faily common one, and one of those bugs that "just can't happen" if the code were according to the specs. But maybe you are already familiar with the prob.

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DanNeely
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I predict chaos when AMD and

I predict chaos when AMD and Intel both have mutually incompatable "SSE5" instruction sets.

After the extended go around over the 80486 moniker back in the 90's though I'm surprised that Intel was willing to use a name that they couldn't control for their x86 extentions.

Dave Burbank
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RE: I predict chaos when

Message 72743 in response to message 72742

Quote:

I predict chaos when AMD and Intel both have mutually incompatable "SSE5" instruction sets.

After the extended go around over the 80486 moniker back in the 90's though I'm surprised that Intel was willing to use a name that they couldn't control for their x86 extentions.

Yeah, same goes for the two companies take on virtualization.

The both want to "set the standard", making life difficult for software developers.

There are 10^11 stars in the galaxy. That used to be a huge number. But it's only a hundred billion. It's less than the national deficit! We used to call them astronomical numbers. Now we should call them economical numbers. - Richard Feynman

Jord
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RE: They both want to "set

Message 72744 in response to message 72743

Quote:
They both want to "set the standard", making life difficult for software developers.


Thereby following hot in the footsteps of choices like CD+R, CD-R, DVD+R, DVD-R, DVD-RAM, DL DVD+R, DL DVD-R, HD DVD and Blu-Ray. What standard? ;-)

th3
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RE: I predict chaos when

Message 72745 in response to message 72742

Quote:
I predict chaos when AMD and Intel both have mutually incompatable "SSE5" instruction sets.


No problem with compatibility, AMDs x86 license gives Intel the right to use any x86 extension AMD might come up with.

ebahapo
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Hey, Intel runs AMD's x86-64

Hey, Intel runs AMD's x86-64 just fine, doesn't it? ;-)

ML1
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RE: Hey, Intel runs AMD's

Message 72747 in response to message 72746

Quote:
Hey, Intel runs AMD's x86-64 just fine, doesn't it? ;-)


And that should be also so for Intel Compiler compiled code for AMDs... Except for Naughty Intel...

(Personally, I think that STINKS.)

Beware Intel's compiler!

Regards,
Martin

See new freedom: Mageia Linux
Take a look for yourself: Linux Format
The Future is what We all make IT (GPLv3)

th3
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Im not paranoid enough to

Im not paranoid enough to think intel deliberately crippled the compiler for AMD, i mean, how much work would THAT be, and could it even be done without losing lots of optimalization for their own processors? To both optimize for their own and at the same time do maximum damage for AMD, thats not realistic at all, but im sure they see it as a nice bonus that it runs so bad on AMDs, same as AMD would if the positions were reversed.

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